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Fast Start Engine IP for New ASIC (Verilog)

Fast Start Engine IP for New ASIC (Verilog)

Client: manufacturer of high-performance GNSS devices

Scope: to create new ASIC microchip for signal processing of GPS/Glonass satellite navigation

Project Features:

  • IP concept development, high-level C++ modeling, verilog implementation and verification
  • Time To First Fix (TTFF) performance optimization via series-parallel logic buildup and signal processing
  • Complex toolchain to merge two different debuggers
  • Highly configurable matched filter which allows seeking different signals with the different types of modulations used in the satellite navigation
  • Special control block for the clock frequency and memory banks usage management to decrease power consumption depending input signal types

Tools & Technologies: Cadence Tools, ModelSim, GNU toolchain, ARM, TMS320 DSP co-processor, debuggers