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Multichannel Hardware Viterbi Decoder IP Implementation (Verilog)

Multichannel Hardware Viterbi Decoder IP Implementation (Verilog)

Client: manufacturer of high-performance GNSS devices

Scope: to create and implement multichannel HW Viterbi Decoder IP from the scratch to increase reception sensitivity without reducing the transmission rate

Project Features:

  • IP concept development
  • High-level C++ model development including verification procedures
  • Verilog implementation
  • Completely HW-controlled (w/o processor or controller involvement)
  • Rigid logic realization
  • More than 180 independent channels
  • Configurable Code Rate (1/2 or 1/3) by external software
  • Configurable polynomial length (6,7,8 or 9) by external software

Tools & Technologies: MS Visual Studio, MatLab, Verilog, C++